The present invention relates to a semiconductor device comprising a Cu wiring and a metal barrier that seamlessly covers outer peripheral portions of a circuit area, and also to a method for manufacturing the semiconductor device.
Semiconductor devices, which are represented by high-performance logic LSIs, require RC delays in transmitted signals to be restrained for fast operations. Thus, as a fine metal wiring material, Cu, which has a low resistance, is gathering much attention instead of conventional Al alloys. In using a Cu wiring, Cu must be prevented from diffusing to areas other than wirings. This is because due to its fast diffusion through an insulating film such as a silicon oxide film, which is commonly used as an interlevel insulating film, Cu may diffuse to a semiconductor element layer to reduce the lifetime of carriers or to degrade the voltage resistance of a gate oxide film. Thus, in the conventional use of a Cu wiring, a nitride of a high-melting-point metal such as TiN or TaN, which has a Cu diffusion preventing function, is combined with an insulating film such as silicon nitride, which also has the same function, to form a diffusion preventing layer around the Cu wiring.
On the other hand, in a semiconductor device, an element layer comprising MOS transistors or the like as well as a multilevel wiring are formed on an Si wafer, which is then cut into chips by means of a dicing step, irrespective of the use of a Cu wiring. During the dicing step, a dicing blade is used to cut a laminate layer consisting of various thin films, so that cracks may occur in a layer with the multilevel wiring formed therein and propagate through the chip to destroy the multilevel wiring layer.
Accordingly, in order to prevent cracks from propagating through the chip if they occur in a cut surface of the chip during the dicing step, known methods form a ring-shaped metal wall inside a dicing area in an outer peripheral portion of the chip which surrounds the chip. This ring-shaped metal wall is formed by forming a ring-shaped pattern both during a multilevel wiring step and during a step of embedding metal in interlevel connection holes (contact or via holes) (the ring-shaped metal wall is hereafter referred to as a "via ring"). That is, in a conventional semiconductor device with a multilevel wiring structure consisting of Al metal wirings formed, for example, by means of a RIE process and W via (contact) plugs formed by embedding W in the connection holes by means of the CVD process, an Al alloy via ring is formed in the outer peripheral portion of the chip during a step of forming an Al alloy thin film into wirings, a ring-shaped groove is subsequently formed on the Al via ring area during a step of forming via holes in the interlevel insulating film, and W is then embedded in the ring-shaped groove to form a w via ring during a step of embedding w in via holes. These steps can be repeated for the number of multilevel wiring levels to form in the multilevel wiring level area the via ring consisting of the Al alloy and the W laminate structure.
The via ring thus formed is effective as a barrier layer that prevents moisture from osmosing from side surfaces of the chip after the dicing. The moisture osmosed into the chip from its side surfaces may corrode the Al alloy constituting the wirings or may cause MOS transistors to malfunction. The use of the via ring structure, however, can prevent these problems.
If, however, Cu is used for the multilevel wirings, the conventional via ring structure and manufacturing method therefor are disadvantageous for the following reasons: according to the conventional via ring manufacturing method, portions of the chip which correspond to the via ring wiring level and via (contact) plugs consist of the Cu covered with a barrier metal. In this case, the barrier metal has a film thickness of 1 to 50 nm, which is much smaller than the sectional dimensions of the via ring. This is because the barrier metal, which has a high resistivity, must have a sufficiently smaller film thickness (or wiring width or via hole diameter) than the Cu, which is the main wiring material, in order to reduce the wiring and via resistances in the multilevel wiring area. Such a thin barrier metal functions as an insufficient crack propagation-preventing layer during the dicing step; if cracks occur, the coverage of the Cu with the barrier metal may be partly destroyed to diffuse the Cu from a break point to the inside of a circuit area (inside the via ring), resulting in the malfunction of transistors.
In addition, if the via ring barrier layer is destroyed in the above manner, the Cu attached to the chip side surface during the dicing step cannot be precluded from diffusing to the inside of the circuit area, resulting in the same problem as described above. Further, the osmosis of moisture through the chip side surface may cause the Cu to oxidize or corrode at the break point of the barrier metal, and the moisture osmosed into the circuit area may oxidize or corrode wirings to affect their operations or may cause the MOS transistors to malfunction.